library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity adder33 is
  port (
    Cin      : in  std_logic;
    A        : in  std_logic_vector(32 downto 0);
    B        : in  std_logic_vector(32 downto 0);
    Sum      : out std_logic_vector(32 downto 0);
    Overflow : out std_logic);
end adder33;

architecture arch of adder33 is
   signal B_t : std_logic_vector(32 downto 0);
   signal t : std_logic_vector(33 downto 0);
   constant n : integer := 33;

   component fulladder
      port(A, B, Cin: in std_logic; Sum, Cout: out std_logic);
    end component;
 
   
begin  -- arch




   B_t <= B when (Cin = '0') else
          not B;

    t(0) <= Cin;
    Overflow <= t(n) xor t(n-1);

    fadd_f: for i in 0 to n-1 generate
      fadd_i : fulladder port map (
        t(i), A(i), B_t(i), Sum(i), t(i+1) );
    end generate;   

end arch;
